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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:15:02 09/18/2013 
-- Design Name: 
-- Module Name:    adder_1bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder_1bit is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C_in : in  STD_LOGIC;
           S : out  STD_LOGIC;
           C_out : out  STD_LOGIC);
end adder_1bit;

architecture Behavioral of adder_1bit is

begin

S <= (not A and not B and C_in) or (not A and B and not C_in) or (A and not B and not C_in) or (A and B and C_in);
C_out <= (B and C_in) or (A and C_in) or (A and B);


end Behavioral;

